This very central research area deals with concepts and techniques for the specific assignment of computing resources to the competing processes and the associated control of the execution of the respective machine programs. Not only are analytical procedures considered, but also constructive approaches are pursued. Tailor-made operating system structures are considered according to the requirements of a respective application domain, either as a proprietary development from scratch or as an extension or adaptation of existing solutions. In functional as well as non-functional terms, the approach is on the one hand application-oriented and on the other hand hardware-centric. The work is mainly characterized by the technology of multi-core or many-core processors and the associated challenges in the coordination of communication and competition of parallel processes.
TRR 89 C1: Invasive Run-Time Support System (iRTSS) (C01)
Teilprojekt C1 erforscht Systemsoftware für invasiv-parallele Anwendungen. Bereitgestellt werden Methoden, Prinzipien und Abstraktionen zur anwendungsgewahren Erweiterung, Konfigurierung und Anpassung invasiver Rechensysteme durch eine neuartige, hochgradig flexible Betriebssystem-Infrastruktur. Diese wird zur praktischen Anwendung in ein Unix-Wirtssystem integriert. Untersucht werden (1) neue Entwurfs- und Implementierungsansätze nebenläufigkeitsgewahrer Betriebssysteme, (2) neuartige AOP-ähnliche Met…
LAOS: Latency Awareness in Operating Systems
The goal of the LAOS project is to investigate in the efficient use of modern many-core processors on operating system level. Thereby providing low latency operating system services even in high contention cases.
Self-made minimal kernels providing thread and interrupt management, as well as synchronization primitives are analyzed with respect to performance and scaling characteristics. These kernels consist of different architectural designs and alternative implementations. Strong focus li…
COKE: Software-controlled consistency and coherence for many-core processor architectures
The achievable computing capacity of individual processors currently strikes at its technological boundary line. Further improvement in performance is attainable only by the use of many computation cores. While processor architectures of up to 16 cores mark the topical state of the art in commercially available products, here and there systems of 100 computing cores are already obtainable. Architectures exceeding thousand computation cores are to be expected in the future. For better scalability,…
TRR 89 C5: Security in Invasive Computing Systems (C05)
Untersucht werden Anforderungen und Mechanismen zum Schutz vor böswilligen Angreifern für ressourcengewahre rekonfigurierbare Hardware/Software-Architekturen. Der Fokus liegt auf der Umsetzung von Informationsflusskontrolle mittels Isolationsmechanismen auf Anwendungs-, Betriebssystems- und Hardwareebene. Ziel der Untersuchungen sind Erkenntnisse über die Wechselwirkungen zwischen Sicherheit und Vorhersagbarkeit kritischer Eigenschaften eines invasiven Rechensystems.
NEON: Non-volatility in energy-aware operating systems
The current trend toward fast, byte-addressable non-volatile memory (NVM) with latencies and write resistance closer to SRAM and DRAM than flash positions NVM as a possible replacement for established volatile technologies. While on the one hand the non-volatility and low leakage capacity make NVM an attractive candidate for new system designs in addition to other advantageous features, on the other hand there are also major challenges, especially for the programming of such systems. For example,…
LARN: Latency and Resilience-aware Networking
The poject develops transport channels for cyber-physical networks. Such channels need to be latency- and resilience-aware; i.e. the latency as seen by the application must be predictable and in certain limits, e.g. by balancing latency and resilience, be guaranteed. This is only possible by an innovative transport protocol stack and an appropriate fundament of operating system and low level networking support. Thereto the current proposal unites the disciplines Operating Systems / Real-Time Processing…
e.LARN: Energy-, Latency- and Resilience-aware Networking
PAVE: Power-fail aware byte-addressable virtual non-volatile memory
Virtual memory (VM) subsystems blur the distinction between storage and memory such that both volatile and non-volatile data can be accessed transparently via CPU instructions. Each and every VM subsystem tries hard to keep highly contended data in fast volatile main memory to mitigate the high access latency of secondary storage, irrespective of whether the data is considered to be volatile or not. The recent advent of byte-addressable NVRAM does not change this scheme in principle, because the…
maRE: Migration-Aware Multi-Core Real-Time Executive
This research proposal investigates the predictability of task migration in multi-core real-time systems. Therefore, we propose , a migration- aware real-time executive where migration decisions are no longer based on generic performance parameters but systematically deduced on application-specific knowledge of the real-time tasks. These so-called migration hints relate to temporal and spatial aspects of real-time tasks; they mark potential migration points in their non- sequential (multi-threaded)…
Nowa: A Wait-Free Continuation-Stealing Concurrency Platform
35th IEEE International Parallel & Distributed Processing Symposium (IPDPS) (Portland, Oregon, 17. May 2021 - 21. May 2021)
In: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS) 2021
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