Aufgabe 5: Zeitscheiben

Classes | Namespaces | Enumerations
core_cr.h File Reference

Access to Control Register of a CPU core. More...

#include "types.h"
+ Include dependency graph for core_cr.h:
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Classes

class  Core::CR< id >
 Access to the Control Register. More...
 

Namespaces

namespace  Core
 Implements an abstraction for CPU internals.
 

Enumerations

enum  Core::CR0 : uintptr_t {
  Core::CR0_PE = 1U << 0 ,
  Core::CR0_MP = 1U << 1 ,
  Core::CR0_EM = 1U << 2 ,
  Core::CR0_TS = 1U << 3 ,
  Core::CR0_ET = 1U << 4 ,
  Core::CR0_NE = 1U << 5 ,
  Core::CR0_WP = 1U << 16 ,
  Core::CR0_AM = 1U << 18 ,
  Core::CR0_NW = 1U << 29 ,
  Core::CR0_CD = 1U << 30 ,
  Core::CR0_PG = 1U << 31
}
 Control Register 0. More...
 
enum  Core::CR4 : uintptr_t {
  Core::CR4_VME = 1U << 0 ,
  Core::CR4_PVI = 1U << 1 ,
  Core::CR4_TSD = 1U << 2 ,
  Core::CR4_DE = 1U << 3 ,
  Core::CR4_PSE = 1U << 4 ,
  Core::CR4_PAE = 1U << 5 ,
  Core::CR4_MCE = 1U << 6 ,
  Core::CR4_PGE = 1U << 7 ,
  Core::CR4_PCE = 1U << 8 ,
  Core::CR4_OSFXSR = 1U << 9 ,
  Core::CR4_OSXMMEXCPT = 1U << 10 ,
  Core::CR4_UMIP = 1U << 11 ,
  Core::CR4_VMXE = 1U << 13 ,
  Core::CR4_SMXE = 1U << 14 ,
  Core::CR4_FSGSBASE = 1U << 16 ,
  Core::CR4_PCIDE = 1U << 17 ,
  Core::CR4_OSXSAVE = 1U << 18 ,
  Core::CR4_SMEP = 1U << 20 ,
  Core::CR4_SMAP = 1U << 21 ,
  Core::CR4_PKE = 1U << 22
}
 Control Register 4. More...
 

Detailed Description

Access to Control Register of a CPU core.