Aufgabe 6: Synchronisation

Constructor for an redirection-table entry.

Every entry in the redirection table represents an external source of interrupts and has a size of 64 bits. Due to the I/O APIC registers being only 32 bits wide, the constructor takes two 32 bit values.

Parameters

value_low	First, low-order 32 bit value
value_high	Second, high-order 32 bit value

The delivery mode denotes the way the interrupts will be delivered to the local CPU cores, respectively to their local APICs.

For StuBS, we use LOWEST_PRIORITY, as all CPU cores have the same priority and we want to distribute interrupts evenly among them. It, however, is not guaranteed that this method of load balancing will work on every system.

The destination mode defines how the value stored in destination will be interpreted.

For StuBS, we use LOGICAL

Delivery status holds the current status of interrupt delivery.

Note

This field is read only; write accesses to this field will be ignored.

The polarity denotes when an interrupt should be issued.

For StuBS, we usually use HIGH (i.e., when the interrupt line is, logically, 1).

The remote IRR bit indicates whether the local APIC(s) accept the level interrupt.

Once the LAPIC sends an End Of Interrupt (EOI), this bit is reset to 0.

Note

This field is read only and is only meaningful for level-triggered interrupts.

The trigger mode states whether the interrupt signaling is level or edge triggered.

StuBS uses EDGE for the Timer, the Keybaord and (optional) serial interface need LEVEL

Mask or unmask interrupts for a particular, external source.

The interrupt mask denotes whether interrupts should be accepted/unmasked (value UNMASKED) or ignored/masked (value MASKED).

Interrupt destination.

The meaning of destination depends on the destination mode: For the logical destination mode, destination holds a bit mask made up of the cores that are candidates for receiving the interrupt. In the single-core case, this value is 1, in the multi-core case, the n low-order bits needs to be set (with n being the number of CPU cores, see Core::count() ). Setting the n low-order bits marks all available cores as candidates for receiving interrupts and thereby balancing the number of interrupts between the cores.

Note

This form of load balancing depends on the hardware's behavior and may not work on all systems in the same fashion. Most notably, in QEMU all interrupts are sent to the BSP (core 0).